MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 863

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
15.6.1.5
This section describes the ten-bit interface (TBI) intended to be used between the PHYs and the eTSEC to
implement a standard SerDes interface for optical-fiber devices in 1000BASE-SX/LX applications.
Figure 15-120
module connection with a PHY. RBC0 and RBC1 are differential 62.5 MHz receive clocks. If not
connected to the TBI PHY, the Signal Detect (SDET) input must be tied high. This causes the eTSEC to
begin auto negotiation with the SERDES immediately upon the TBI module being enabled.
A TBI interface has 26 signals (GE_GTX_CLK125 included) for connecting to an Ethernet PHY, as
defined by IEEE 802.3z GMII and TBI standards.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’
connections in the system, assuming that each PHY has a different management address.
eTSEC
Ten-Bit Interface (TBI)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
depicts the basic components of the TBI including the signals required to establish eTSEC
GigaBit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
TBI Receive Clock 0 (TSEC n _RX_CLK)
TBI Receive Clock 1 (TSEC n _TX_CLK)
SIGNAL DETECT (TSEC n _RX_CRS)
Figure 15-120. eTSEC-TBI Connection
Transmit Data (TSEC n _TXD[9:0])
Receive Data (TSEC n _RXD[9:0])
Management Data Clock
Management Data I/O
1
1
(MDIO)
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
Gigabit
PHY
Medium
15-131

Related parts for MPC8544VTALF