MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 362

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 9-33
9.4.1.28
The memory error attributes capture register, shown in
type, size, source, and others.
Table 9-34
9-38
25–27
0–23
Bits
Bits
1–3
24
28
29
30
31
Offset 0xE4C
Reset
0
4
W
R
BNUM Data beat number. Captures the doubleword number for the detected error. Relevant only for ECC errors.
MBEE Multiple-bit ECC error interrupt enable. Note that uncorrectable read errors may cause the assertion of
MSEE Memory select error interrupt enable
Name
ACEE Automatic calibration error interrupt enable
SBEE Single-bit ECC error interrupt enable
Name
—
0
—
—
—
—
—
describes the ERR_INT_EN fields.
describes the CAPTURE_ATTRIBUTES fields.
1
Figure 9-29. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)
BNUM
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
0 Automatic calibration errors cannot generate interrupts.
1 Automatic calibration errors generate interrupts.
Reserved
core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, MBEE and ERR_DISABLE[MBED] must be zero and
DDR_SDRAM_CFG[ECC_EN] must be set to ensure that an interrupt is generated. For more information, see
Section 6.10.2, “Hardware Implementation-Dependent Register 1
0 Multiple-bit ECC errors cannot generate interrupts.
1 Multiple-bit ECC errors generate interrupts.
0 Single-bit ECC errors cannot generate interrupts.
1 Single-bit ECC errors generate interrupts.
Reserved
0 Memory select errors do not cause interrupts.
1 Memory select errors generate interrupts.
Reserved
Reserved
3
—
4
Table 9-34. CAPTURE_ATTRIBUTES Field Descriptions
5
TSIZ
Table 9-33. ERR_INT_EN Field Descriptions
7
8
—
10 11
TSRC
All zeros
15 16 17 18 19 20
Description
Description
Figure
—
9-29, sets attributes for errors including
TTYP
(HID1).”
—
Freescale Semiconductor
Access: Read/Write
30
VLD
31