MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 28

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
15.5.3.3.7
15.5.3.3.8
15.5.3.3.9
15.5.3.3.10
15.5.3.3.11
15.5.3.3.12
15.5.3.3.13
15.5.3.4
15.5.3.4.1
15.5.3.4.2
15.5.3.4.3
15.5.3.4.4
15.5.3.4.5
15.5.3.5
15.5.3.5.1
15.5.3.5.2
15.5.3.5.3
15.5.3.5.4
15.5.3.5.5
15.5.3.5.6
15.5.3.5.7
15.5.3.5.8
15.5.3.5.9
15.5.3.5.10
15.5.3.5.11
15.5.3.5.12
15.5.3.5.13
15.5.3.5.14
15.5.3.5.15
15.5.3.5.16
15.5.3.6
15.5.3.6.1
15.5.3.6.2
15.5.3.6.3
15.5.3.6.4
15.5.3.6.5
15.5.3.6.6
15.5.3.6.7
xxviii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAC Functionality.............................................................................................. 15-65
MAC Registers .................................................................................................... 15-67
MIB Registers...................................................................................................... 15-80
Receive Queue Filer Table Control Register (RQFCR) .................................. 15-58
Receive Queue Filer Table Property Register (RQFPR) ................................. 15-59
Maximum Receive Buffer Length Register (MRBLR) ................................... 15-62
Receive Data Buffer Pointer High Register (RBDBPH) ................................. 15-62
Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) ....................... 15-63
Receive Descriptor Base Address High Register (RBASEH)......................... 15-64
Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 15-64
Configuring the MAC ..................................................................................... 15-65
Controlling CSMA/CD.................................................................................... 15-65
Handling Packet Collisions ............................................................................ 15-65
Controlling Packet Flow.................................................................................. 15-66
Controlling PHY Links.................................................................................... 15-67
MAC Configuration 1 Register (MACCFG1)................................................. 15-67
MAC Configuration 2 Register (MACCFG2)................................................. 15-69
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 15-71
Half-Duplex Register (HAFDUP) ................................................................... 15-72
Maximum Frame Length Register (MAXFRM) ............................................. 15-73
MII Management Configuration Register (MIIMCFG) .................................. 15-73
MII Management Command Register (MIIMCOM)....................................... 15-74
MII Management Address Register (MIIMADD)........................................... 15-75
MII Management Control Register (MIIMCON)............................................ 15-75
MII Management Status Register (MIIMSTAT) ............................................. 15-76
MII Management Indicator Register (MIIMIND)........................................... 15-76
Interface Status Register (IFSTAT).................................................................. 15-77
MAC Station Address Part 1 Register (MACSTNADDR1) ........................... 15-77
MAC Station Address Part 2 Register (MACSTNADDR2) ........................... 15-78
MAC Exact Match Address 1–15 Part 1 Registers
MAC Exact Match Address 1–15 Part 2 Registers
Transmit and Receive 64-Byte Frame Counter (TR64) .................................. 15-80
Transmit and Receive 65- to 127-Byte Frame Counter (TR127) .................... 15-81
Transmit and Receive 128- to 255-Byte Frame Counter (TR255) .................. 15-81
Transmit and Receive 256- to 511-Byte Frame Counter (TR511) .................. 15-82
Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ................. 15-82
Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)........... 15-83
Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter
(MAC01ADDR1–MAC15ADDR1)............................................................ 15-79
(MAC01ADDR2–MAC15ADDR2)............................................................ 15-79
(TRMGV) .................................................................................................... 15-83
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