MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1104

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
18.3.8.1.10 PCI Express BIST Register—0x0F
The BIST register is optional and reserved on the PCI Express controller.
18.3.8.2
The type 0 header is shown in
Section 18.3.8.1, “Common PCI Compatible Configuration Header
the first 16 bytes of the header. This section describes the registers that are unique to the type 0 header
beginning at offset 0x10.
18.3.8.2.1
The PCI Express base address registers (BARs) point to the beginning of distinct address ranges which the
device should claim. In EP mode, the device supports a configuration space BAR, a 32-bit memory space
BAR, and two 64-bit memory space BARs. In RC mode, the device only supports the configuration space
BAR in the header; the other memory spaces are defined by the inbound ATMUs. Refer to
Section 18.3.5.2, “PCI Express Inbound ATMU
Base address register 0 at offset 0x10 is a special fixed 1-Mbyte window that is used for inbound
configuration accesses. This window is called the PCI Express configuration and status register base
address register (PEXCSRBAR). Note that PEXCSRBAR cannot be updated through the inbound ATMU
registers. The PEXCSRBAR is shown in
18-50
Reserved
MAX_LAT
BIST
Type 0 Configuration Header
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Base Address Registers—0x10–0x27
Figure 18-46. PCI Express PCI-Compatible Configuration Header—Type 0
Subsystem ID
Device ID
Status
Figure
Header Type
Class Code
MIN_GNT
18-46.
Expansion ROM Base Address
Base Address Registers
Figure
Registers,” for more information.
18-47.
Latency Timer
Interrupt Pin
Subsystem Vendor ID
Registers,” describes the registers in
Command
Vendor ID
Capabilities Pointer
Cache Line Size
Interrupt Line
Revision ID
Freescale Semiconductor
Offset (Hex)
Address
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C