MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 872

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
The encoding of the eTSEC GMII signals in this FIFO mode is shown in
In this mode flow control can control only the decision to continue transmitting packets, as packet transfers
cannot be suspended once started.
15.6.2.4
The encoded packet 8-bit FIFO mode uses the signals shown in
four states that can be associated with each beat of data. This mode should be used where invalid bytes can
appear between the start and end of packet. Illustrative timing of the encoded packet FIFO mode is shown
in
The encoding of the eTSEC GMII signals in this FIFO mode is shown in
In this mode flow control can cause an indefinite number of invalid data bytes to be transferred. This is the
only mode in which an empty eTSEC Tx FIFO also causes a string of invalid data bytes to be transmitted
rather than causing an underrun error.
15.6.2.5
Refer to
15-140
Figure
Section 15.7.1.7, “8-Bit FIFO Mode”
15-124.
Valid data, start of packet
Valid data
Valid data, end of packet
Error
8-Bit Encoded Packet FIFO Mode
FIFO Interface Signal Summary
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TX_ER/RX_ER
TX_EN/RX_DV
Valid data, start of packet
Valid data
Valid data, end of packet
Data not valid
TXD/RXD[7:0]
TX/RX_CLK n
Condition
Table 15-128. Signal Encoding for GMII-Style 8-Bit FIFO
Condition
Table 15-129. Signal Encoding for Encoded 8-Bit FIFO
Figure 15-124. 8-Bit Encoded Packet FIFO Timing
SOP
0 to 1 transition at start of cycle
1 to 0 transition at end of cycle
for interface signal details.
TX_EN/RX_DV
TX_EN/RX_DV
1
1
1
1
0
0
Figure
1 until TX_EN/RX_DV falls
TX_ER/RX_ER
15-124. The control lines encode
EOP
Table
Table
TX_ER/RX_ER
0
1
1
0
15-128.
15-129.
0
0
0
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