MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 446

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
Table 10-50
10.3.8.5
Writing to the end of interrupt (EOI) register shown in
highest-priority interrupt currently in-service by the processor. The write to the EOI updates the ISR by
retiring the highest priority interrupt. Data values written to this register are ignored, and zero is assumed.
Table 10-51
10.4
This section is a functional description of the PIC.
10.4.1
Figure 10-48
intended to aid in understanding and does not fully represent all internal circuitry of the actual
implementation. The PIC receives interrupt signals from both external and internal sources. These signals
are qualified and latched in the interrupt pending register (IPR). The IPR feeds the interrupt selector (IS).
The interrupt router of the PIC monitors the outputs of its internal interrupt request register (IRR) and other
configuration registers. When the priority of the interrupt latched in the IRR is higher than the value in the
10-48
16–31
28–31
0–15
0–27
Offset 0x6_00B0
Bits
Reset
Bits
W
R
0
VECTOR
EOI CODE
Name
Name
Functional Description
—
—
describes the IACK fields.
describes the EOI fields.
Flow of Interrupt Control
is a block diagram of the PIC unit showing the flow of interrupt processing. This figure is
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Processor End of Interrupt Register (EOI)
Reserved
Interrupt vector. Vector of the highest pending interrupt (read only)
Reserved
0000 (write only)
Figure 10-47. End of Interrupt Register (EOI)
Table 10-50. IACK Field Descriptions
Table 10-51. EOI Field Descriptions
—
All zeros
Figure 10-47
Description
Description
signals the end of processing for the
Freescale Semiconductor
Access: Write only
27 28
EOI CODE
31