MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1106

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 18-46
Base address register 3 at offset 0x1C and base address register 5 at offset 0x24 are used to define the upper
portion of the 64-bit inbound memory windows. The 64-bit high memory BARs are shown in
Figure
Table 18-47
18-52
31–0 ADDRESS Indicates the upper portion of the base address where the inbound memory window begins. The number of
31–12 ADDRESS Indicates the lower portion of the base address where the inbound memory window begins. The number
Bits
11–4
Bits
2–1
3
0
Offset 0x18 (EP-mode only)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Offset 0x1C (EP-mode only)
Reset
W
18-50.
R
W
R
Name
MemSp
0x20 (EP-mode only)
31
Name
PREF
TYPE
0x24 (EP-mode only)
31
—
describes the PCI Express 64-bit low memory BAR fields.
describes the PCI Express 64-bit low memory BAR fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 18-46. 64-Bit Low Memory Base Address Register Field Descriptions
bits that the device allows to be writable is selected through the inbound window size in the inbound window
attributes registers (PEXIWAR2 for offset 0x1C and PEXIWAR3 for offset 0x24). If no access to local memory
is to be permitted by external requestors, then all bits are programmed.
Table 18-47. Bit Setting for 64-Bit High Memory Base Address Register
of bits that the device allows to be writable is selected through the inbound window size in the inbound
window attributes registers (PEXIWAR2 for offset 0x18 and PEXIWAR3 for offset 0x20).
Reserved. The device allows a 4 Kbyte window minimum.
Prefetchable. This bit is determined by PEXIWAR n [2].
Type.
0b10 Locate anywhere in 64-bit address space.
Memory space indicator
Figure 18-50. 64-Bit High Memory Base Address Register
Figure 18-49. 64-Bit Low Memory Base Address Register
ADDRESS
ADDRESS
All zeros
Description
Description
12 11
—
4
PREF
3
1
Freescale Semiconductor
Access: Read/Write
2
1
TYPE
Access: Mixed
0
1
MemSp
0
0
0