MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 438

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
10.3.7.2
The external interrupt destination registers (EIDRs), shown in
external interrupts caused by the assertion of any of IRQ[0:11]. All external interrupts are directed to the
processor 0 interrupt, int, by default. External interrupts can be selectively directed to IRQ_OUT or to the
processor 0 critical interrupt signal, cint, instead of int by writing to the appropriate EIDRn fields.
Table 10-41
the P0 bit is permanently set. As shown in
not sent to the processor’s interrupt input.
The EP or CI fields must be set only for level-sensitive interrupts. Setting these fields for edge-sensitive
interrupts does not provide reliable interrupt response.
10-40
10–11
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector. Contains the value returned when the interrupt acknowledge (IACK) register is read and this interrupt
Offset EIDR0 0x5_0010, EIDR1 0x5_0030, EIDR2 0x5_0050, EIDR3 0x5_0070, EIDR4 0x5_0090, EIDR5
Reset 0
Bits Name
Bits
0
1
W
R
0x5_00B0, EIDR6 0x5_00D0, EIDR7 0x5_00F0, EIDR8 0x5_0110, EIDR9 0x5_0130, EIDR10 0x5_0150,
EIDR11 0x5_0170
EP CI
EP
0
CI
Name
—
0
1
External pin. Allows external interrupt to be serviced externally.
0 External interrupt is serviced internally with int signal to the processor core.
1 External interrupt is directed to IRQ_OUT for external service.
Critical interrupt.
0 External interrupt is serviced internally with int signal to the processor core.
1 External interrupt is directed to processor 0 as a critical interrupt with the cint signal.
describes the EIDR fields. Because external interrupts can be channeled only to processor 0,
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Interrupt Destination Registers (EIDR0–EIDR11)
The behavior of the PIC unit is not defined if both the EP and CI bits of the
same interrupt destination register are set.
0
2
Reserved.
of 0 disables interrupts from this source.
resides in the interrupt request register (IRR) shown in
0
Figure 10-37. External Interrupt Destination Registers (EIDRs)
0 0
Table 10-40. EIVPR n Field Descriptions (continued)
0
0 0
Table 10-41. EIDR n Field Descriptions
0
0 0
Figure
0
NOTE
0 0
10-48, if either the CI or EP bits are set, the interrupt is
Description
Description
0
—
0 0
Figure
Figure
0
0 0
10-48.
10-37, control the destination of
0
0 0
0
Freescale Semiconductor
0
0 0
0 0 0
Access:
30 31
Mixed
P0
1