MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 738

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.4
This section defines the eTSEC interface signals. The buses are described using the bus convention used
in IEEE 802.3 because the PHY follows this same convention. (That is, TxD[7:0] means 0 is the lsb.) Note
that except for external physical interfaces the buses and registers follow a big-endian format, where 0
denotes the msb.
Each eTSEC network interface supports multiple options:
15-6
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Received frames are by default sent to a single buffer descriptor ring. If multiple receive queues
are enabled, a receive queue filer can be programmed with selection criteria to differentiate
received frames and file them to different buffer descriptor rings. See
Service (QoS) Provision,”
TCP/IP transmit options
Frames for transmission may be sent as-is, with IP header processing, or TCP header processing.
The transmit buffer descriptors, described in
(TxBD),”
described in
Transmit queue selection options
The options supported are single transmit queue, priority-based queue selection, and modified
weighted round-robin queueing. These options are described further in
“Transmit Control Register (TCTRL).”
RMON support
Standard Ethernet interface management information base (MIBs) can be generated via the RMON
MIB counters.
Internal loop back supported for all interfaces except when configured for half-duplex operation
Internal loop back mode is selected via the loop back bit in the MACCFG1 register. See
Section 15.7.1, “Interface Mode Configuration,”
The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
The GMII option is a superset of the MII signals and supports a 1000-Mbps Ethernet rate.
The TBI interface shares signals with the GMII interface signals.
The RGMII, RTBI, and RMII options are reduced-pin implementations of the GMII, TBI, and MII
interfaces, respectively.
SGMII interfaces are offered via the SD2 SerDes interface signals.
Finally, the FIFO interfaces share the GMII signals—8 bits of data plus 3 bits of control signals.
External Signals Description
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
enable these options and operate with parameters prepended to frame buffers, as
Section 15.6.4, “TCP/IP Off-Load.”
for detailed descriptions.
Section 15.6.7.2, “Transmit Data Buffer Descriptors
for details.
Section 15.6.5, “Quality of
Section 15.5.3.2.1,
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