MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 729

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Synchronous Single Read
Figure 14-88
The DSI samples HA, HDST, HCID, HWBE, HRDE, and HBRST on the first HCLKIN rising edge on
which HCS is asserted. If the HCID[0:3] signals match the CHIPID value, the DSI is accessed. HRDE is
asserted, and HWBE and HBRST are negated. If DCR[8]:RPE is set (see MSC8102 documentation), read
access to the memory space (not to the register space) initiates prefetching data from consecutive addresses
in the internal memory space. Assertion of HTA indicates that data is valid and the host must sample the
HD and terminate the access. Because HTA is connected to the UPM LUPWAIT signal, all local bus
signals are frozen until HTA goes to 0; then the UPM continues in its pattern. HTA is asserted earlier when
the data for this access is already prefetched to the read buffer. It asserted for one HCLKIN cycle and
driven to logic 1 in the next cycle. It stops being driven on the next rising edge of HCLKIN. The host can
start its next access to the same MSC8102 immediately in the next HCLKIN rising edge without negating
HCS between accesses. If the next access is not to the same MSC8102, then, to prevent contention on HTA,
the host must wait to access the next device until the previous DSI stops driving HTA. The easiest way to
achieve this is to insert idle cycles at the end of the UPM pattern to guarantee that HTA is inactive.
Freescale Semiconductor
HWBE[0:7]
Legend:
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
shows a synchronous single read access.
HD[0:63]
1
0
1
0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
HCLKIN
HBRST
HRDE
HCS
HTA
Figure 14-88. Synchronous Single Read from MSC8102 DSI
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Local Bus Controller
14-109