MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 264

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Register Summary
6-46
40–41
Bits
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
FUNFH Embedded floating-point underflow error high
FOVFH Embedded floating-point overflow error high
FDBZH Embedded floating-point divide by zero error high. Set if the dividend is non-zero and the divisor is zero.
FDBZS Embedded floating-point divide by zero sticky. FDBZS = FDBZS | FDBZH | FDBZ
FUNFS Embedded floating-point underflow sticky. Storage location for software to use when implementing true
FOVFS Embedded floating-point overflow sticky. Storage location for software to use when implementing true IEEE
FINVH
MODE
FINXS
FINVS
FINXE
Name
FDBZ
FUNF
FOVF
FINV
FGH
SOV
FXH
OV
FG
FX
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is undefined
if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
or Denorm. Also set on a divide if both the dividend and divisor are zero.
Reserved, should be cleared.
floating point.
IEEE floating point.
floating point.
it is cleared by mtspr[SPEFSCR].
Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction is
being executed.
Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined if the
processor takes a floating-point exception due to input error, floating-point overflow, or floating-point
underflow.
Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the processor
takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow.
Denorm. Also set on a divide if both the dividend and divisor are zero.
Reserved, should be cleared.
Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the
Embedded floating-point invalid operation error high. Set when an input value on the high side is a NaN, Inf,
Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX
Embedded floating-point invalid operation sticky. Location for software to use when implementing true IEEE
Embedded floating-point mode (read only on e500)
Integer summary overflow. Set whenever an SPE instruction (except mtspr) sets OV. SOV remains set until
Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN, Inf, or
Embedded floating-point divide by zero error. Set of the dividend is non-zero and the divisor is zero.
Embedded floating-point underflow error
Embedded floating-point overflow error
Embedded floating-point inexact enable
Table 6-39. SPEFSCR Field Descriptions (continued)
Function
Freescale Semiconductor