MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 540

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Security Engine (SEC) 2.1
12.4.4.11 MDEU Context Registers
For the MDEU, the context consists of the hash plus the message length count. Write access to this register
block allows continuation of a previous hash. Reading these registers provide the resulting message digest
or HMAC, along with an aggregate bit count.
After a power-on reset, all the MDEU context register values are cleared to 0.
MDEU context registers are initialized if the INIT bit is set in the MDEU mode register.
12-60
Address MDEU 0x3_6050
Reset
W
R
0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SHA-1and SHA-256 are big endian. MD5 is little endian. The MDEU
module internally reverses the endianness of the five registers A, B, C, D,
and E upon writing to or reading from the MDEU context if the MDEU
mode register indicates MD5 is the hash of choice. Most other endian
considerations are performed as 8-byte swaps. In this case, 4-byte
endianness swapping is performed within the A, B, C, D, and E fields as
individual registers. Reading this memory location while the module is not
done will generate an error interrupt.
Figure 12-38. MDEU EU Go Register
NOTE
All zeros
Figure 12-39
Freescale Semiconductor
Access: Write-only
shows how the
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