MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 91

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Part IV, “Global Functions and Debug,” defines other global blocks of the MPC8544E. The following
chapters are included:
This manual contains the following appendixes:
This reference manual contains a glossary and a general index.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor,
San Francisco, CA, provides useful information about the PowerPC™ architecture and computer
architecture in general:
Freescale Semiconductor
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captive DMA channel and direct connection to the MPC8544E memory coherency module. The
controllers provide two full-duplex FIFO interface modes and quality of service support. They are
backward compatible with PowerQUICC™ III TSEC controllers.
Chapter 16, “DMA Controller,”
MPC8544E. The DMA controller transfers blocks of data independent of the e500v2 core or
external hosts. Data movement occurs among the local address space. The DMA controller has four
high-speed channels. Both the e500 core and external masters can initiate a DMA transfer. All
channels are capable of complex data movement and advanced transaction chaining.
Chapter 17, “PCI Bus Interface,”
Chapter 18, “PCI Express Interface
MPC8544E.
Chapter 19, “Global Utilities,”
management, I/O device enabling, power-on-reset (POR) configuration monitoring,
general-purpose I/O signal use, and multiplexing for the interrupt and local bus chip select signals.
Chapter 20, “Device Performance Monitor,”
MPC8544E. Note that the device performance monitor is similar to but separate from the
performance monitor on the e500v2 core.
Chapter 21, “Debug Features and Watchpoint Facility,”
watchpoint monitor of the MPC8544E.
Appendix A, “Revision History,”
PowerQUICC III Integrated Host Processor Family Reference Manual.
Appendix B, “Complete List of Configuration, Control, and Status Registers,”
listing of the memory-mapped registers of the MPC8544E.
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
defines the global utilities of the MPC8544E. These include power
describes the four-channel general-purpose DMA controller of the
describes the PCI controller of the MPC8544E.
lists the major differences between revisions of the MPC8544E
Controller,” describes the PCI-Express implementation of the
describes the performance monitor of the
describes the debug features and
contains a complete
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