MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1179

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.1.10 General-Purpose Input Data Register (GPINDR)
GPINDR, shown in
pins.
Table 19-12
19.4.1.11 Alternate Function Signal Multiplex Control Register (PMUXCR)
Shown in
functions on local bus chip select pins LCS[5:7], and interrupt input pins IRQ[9:11], respectively.
Specifically, DMA request, acknowledge, and done signals comprise the secondary functions for the
associated IRQ and local bus chip select signals.
Freescale Semiconductor
Offset 0xE_0060
Reset
Offset 0xE_0050
Reset n
8–31
Bits
0–7
W
R
W
R
0
0
Name
GPIN General-purpose input data. The values of the bits of field GPINDR[0:7] are reflected onto pins GPIN[0:7] as
—
Figure
n
describes the fields of GPINDR.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
n
follows:
Reserved
Figure 19-11. Alternate Function Pin Multiplex Control Register (PMUXCR)
GPIN
19-11, PMUXCR contains bits that enable DMA channels 2 and 3 which exist as alternate
n
GPINDR[0] ↔ GPIN[0]
GPINDR[1] ↔ GPIN[1]
GPINDR[2] ↔ GPIN[2]
GPINDR[3] ↔ GPIN[3]
GPINDR[4] ↔ GPIN[4]
GPINDR[5] ↔ GPIN[5]
GPINDR[6] ↔ GPIN[6]
GPINDR[7] ↔ GPIN[7]
Figure
n n
Figure 19-10. General-Purpose Input Data Register (GPINDR)
—
n
19-10, contains the data currently sampled as general-purpose input on GPIN
n 0
7
8
Table 19-13. GPINDR Field Descriptions
0
0
0
0
14
0
DMA2
0
15
All zeros
0
Description
16
0
0
0
0
—
0
0
0
—
0
0
0
0
Access: Read Only
Access: Read/Write
0
0
Global Utilities
0
30
0
DMA3
19-13
31
31
0