MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1176

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Global Utilities
19.4.1.5
PORDBGMSR, shown in
described in
Configuration,”
Table 19-8
19.4.1.6
Figure 19-6
19-10
7–31
Bits
0–4
Offset 0xE_0014
Reset n 0 0 0 n n n n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
5
6
Offset 0xE_0010
Reset 0 0 0 0
W
R
W
R
MEM_SEL Memory select. Indicates which controller is driving MSRCID[0:4] and MDVAL.
DDR_DBG DDR debug configuration
0
0
Name
—
—
describes the bit settings of PORDBGMSR.
describes the bit settings of PORDEVSR2.
Section 4.4.3.20, “Memory Debug Configuration,” Section 4.4.3.21, “DDR Debug
POR Debug Mode Status Register (PORDBGMSR)
POR Device Status Register 2 (PORDEVSR2)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
and
Reserved
0 Local bus controller is driving debug information
1 DDR SDRAM controller is driving debug information
0 SourceID and data valid information is being driven on ECC pins of DDR SDRAM interface
1 Normal mode. ECC information is being driven on ECC pins of DDR SDRAM interface
Reserved
—
Section 4.4.3.22, “PCI Debug Configuration.”
Figure 19-5. POR Debug Mode Status Register (PORDBGMSR)
0
4
Figure 19-6. POR Device Status Register 2 (PORDEVSR2)
Figure
Table 19-8. PORDBGMSR Field Descriptions
MEM_SEL
19-5, holds debug mode settings from the POR configuration pins as
n
5
—
DDR_DBG
6
n
Description
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7
25
—
SEC_CFG
Freescale Semiconductor
26
n
Access: Read Only
Access: Read Only
27
1 1 1 n n
—
31
31