MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 27

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
15.1
15.2
15.3
15.4
15.4.1
15.5
15.5.1
15.5.2
15.5.3
15.5.3.1
15.5.3.1.1
15.5.3.1.2
15.5.3.1.3
15.5.3.1.4
15.5.3.1.5
15.5.3.1.6
15.5.3.1.7
15.5.3.1.8
15.5.3.1.9
15.5.3.2
15.5.3.2.1
15.5.3.2.2
15.5.3.2.3
15.5.3.2.4
15.5.3.2.5
15.5.3.2.6
15.5.3.2.7
15.5.3.2.8
15.5.3.2.9
15.5.3.2.10
15.5.3.2.11
15.5.3.3
15.5.3.3.1
15.5.3.3.2
15.5.3.3.3
15.5.3.3.4
15.5.3.3.5
15.5.3.3.6
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview........................................................................................................................ 15-1
Features .......................................................................................................................... 15-2
Modes of Operation ....................................................................................................... 15-4
External Signals Description ......................................................................................... 15-6
Memory Map/Register Definition ............................................................................... 15-13
Detailed Signal Descriptions ..................................................................................... 15-8
Top-Level Module Memory Map ............................................................................ 15-13
Detailed Memory Map............................................................................................. 15-14
Memory-Mapped Register Descriptions.................................................................. 15-23
eTSEC General Control and Status Registers...................................................... 15-23
eTSEC Transmit Control and Status Registers.................................................... 15-37
eTSEC Receive Control and Status Registers ..................................................... 15-49
Controller ID Register (TSEC_ID).................................................................. 15-23
Controller ID Register (TSEC_ID2)................................................................ 15-24
Interrupt Event Register (IEVENT) ................................................................ 15-24
Interrupt Mask Register (IMASK) .................................................................. 15-28
Error Disabled Register (EDIS)....................................................................... 15-30
Ethernet Control Register (ECNTRL) ............................................................. 15-32
Pause Time Value Register (PTV) ................................................................... 15-34
DMA Control Register (DMACTRL) ............................................................. 15-35
TBI Physical Address Register (TBIPA) ......................................................... 15-36
Transmit Control Register (TCTRL) ............................................................... 15-37
Transmit Status Register (TSTAT)................................................................... 15-39
Default VLAN Control Word Register (DFVLAN) ........................................ 15-43
Transmit Interrupt Coalescing Register (TXIC).............................................. 15-44
Transmit Queue Control Register (TQUEUE) ................................................ 15-45
TxBD Ring 0–3 Weighting Register (TR03WT)............................................. 15-45
TxBD Ring 4–7 Weighting Register (TR47WT)............................................. 15-46
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 15-47
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 15-47
Transmit Descriptor Base Address High Register (TBASEH)........................ 15-48
Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 15-49
Receive Control Register (RCTRL) ................................................................ 15-49
Receive Status Register (RSTAT).................................................................... 15-51
Receive Interrupt Coalescing Register (RXIC) ............................................... 15-53
Receive Queue Control Register (RQUEUE) ................................................. 15-54
Receive Bit Field Extract Control Register (RBIFX)...................................... 15-56
Receive Queue Filer Table Address Register (RQFAR) ................................. 15-57
Enhanced Three-Speed Ethernet Controllers
Contents
Chapter 15
Title
Number
Page
xxvii