MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1203

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.1.2
The performance monitor offers a rich set of features that permits a complete performance characterization
of the implementation. These features include:
20.2
The performance monitor does not have any signals that are driven externally (off-chip) but it does assert
the internal interrupt (int) signal on a performance monitor interrupt condition.
20.3
Performance monitor registers reside in the run-time register block starting at offset 0xE_1000. Undefined
4-byte address spaces within offset 0x000–0xFFF are reserved. This section describes the registers
implemented to support the performance monitor facilities.
registers. These registers can be read or written only with 32-bit accesses.
20.3.1
The performance monitor uses ten counter registers and a group of local control registers that are used to
specify the method of counting. Two local control registers are associated with each counter in addition to
a global control register that applies to all counters.
In this table and in the register figures and field descriptions, the following access definitions apply:
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One 64-bit counter exclusively dedicated to counting cycles
Nine 32-bit counters that count the occurrence of selected events
One global control register (affects all counters) and two local control registers per counter
Ability to count up to 64 reference events that may be counted on any of the nine 32-bit counters
Ability to count up to 576 counter-specific events
Triggering and chaining capability
Duration and quantity threshold counting
Burstiness feature that permits counting of burst events with a programmable time between bursts
Ability to generate an interrupt on overflow
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Signal Descriptions
Memory Map and Register Definition
Features
Register Summary
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-1
lists the performance monitor
Device Performance Monitor
20-3