MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 32

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
15.6.5.1.8
15.6.5.2
15.6.5.2.1
15.6.5.2.2
15.6.6
15.6.6.1
15.6.6.2
15.6.6.2.1
15.6.6.2.2
15.6.7
15.6.7.1
15.6.7.2
15.6.7.3
15.7
15.7.1
15.7.1.1
15.7.1.2
15.7.1.3
15.7.1.4
15.7.1.5
15.7.1.6
15.7.1.7
15.7.1.8
16.1
16.1.1
16.1.2
16.1.3
16.1.4
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.1.1
16.3.1.2
16.3.1.3
xxxii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization/Application Information ....................................................................... 15-179
Introduction.................................................................................................................... 16-1
External Signal Description ........................................................................................... 16-5
Memory Map/Register Definition ................................................................................. 16-6
Lossless Flow Control ........................................................................................... 15-170
Buffer Descriptors.................................................................................................. 15-173
Interface Mode Configuration ............................................................................... 15-179
Block Diagram........................................................................................................... 16-1
Overview.................................................................................................................... 16-2
Features...................................................................................................................... 16-2
Modes of Operation ................................................................................................... 16-2
Signal Overview ........................................................................................................ 16-5
Detailed Signal Descriptions ..................................................................................... 16-6
DMA Register Descriptions....................................................................................... 16-9
Transmission Scheduling................................................................................... 15-168
Back Pressure Determination via Free Buffers.................................................. 15-170
Data Buffer Descriptors ..................................................................................... 15-173
Transmit Data Buffer Descriptors (TxBD) ........................................................ 15-174
Receive Buffer Descriptors (RxBD).................................................................. 15-177
MII Interface Mode............................................................................................ 15-180
GMII Interface Mode......................................................................................... 15-184
TBI Interface Mode ........................................................................................... 15-188
RGMII Interface Mode ...................................................................................... 15-192
RMII Interface Mode......................................................................................... 15-196
RTBI Interface Mode......................................................................................... 15-200
8-Bit FIFO Mode ............................................................................................... 15-204
SGMII Interface Support ................................................................................... 15-206
Mode Registers (MRn) ........................................................................................ 16-10
Status Registers (SRn) ......................................................................................... 16-12
Current Link Descriptor Address Registers (CLNDARn and
Software Use of Hardware-Initiated Back Pressure .......................................... 15-172
Filer Example—TCP and UDP Port Filing .................................................. 15-167
Priority-Based Queuing (PBQ)...................................................................... 15-168
Modified Weighted Round-Robin Queuing (MWRR) .................................. 15-169
Initialization................................................................................................... 15-172
Operation ....................................................................................................... 15-172
ECLNDARn) ................................................................................................... 16-13
DMA Controller
Contents
Chapter 16
Title
Freescale Semiconductor
Number
Page