MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 790

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-31
15.5.3.3.7
RQFCR is accessed to read or write the RQCTRL words in entries of the receive queue filer table. The
table entries are described in greater detail in
via RQFCR is defined by the current value of RQFAR.
Figure 15-28
Table 15-32
15-58
24–31
16–21
Offset eTSEC1:0x2_4338; eTSEC3:0x2_5338
Reset
0–23
0–15
Bits
Bit
22
23
24
W
R
0
Name
RQFAR Current index of receive queue filer table, which spans a total of 256 entries.
AND
Name
CLE
REJ
—
Q
—
describes the fields of the RQFAR register.
describes the fields of the RQFCR register.
describes the definition for the RQFCR register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Queue Filer Table Control Register (RQFCR)
Reserved, should be written with zero.
Receive queue index, from 0 to 63, inclusive, written into the Rx frame control block associated with the
received frame. When a property matches the value in the RQPROP entry at this index, and REJ = 0 and
AND = 0, the frame is sent to either RxBD ring 0 (if RCTRL[FSQEN] = 1) or the RxBD ring with index (Q mod
8) and the filing table search is terminated. In the case where RCTRL[FSQEN] = 0, 8 virtual receive queues
are overlaid on every RxBD ring, and software needs to consult the RQ field of the Rx frame control block to
determine which virtual receive queue was chosen.
Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end
entries of a cluster. Clusters cannot be nested.
0 Regular RQCTRL entry.
1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the
Reject frame. This bit and its specified action are ignored if AND = 1.
0 If entry matches, accept frame and file it to RxBD ring Q.
1 If entry matches, reject frame and discard it, ignoring Q.
Match this entry and the next entry as a pair.
0 Match property[PID] against RQPROP, independent of the next entry.
1 Match property[PID] against RQPROP. If matched and CLE = 0, attempt to match next entry, otherwise,
Reserved
cluster; otherwise skip all entries up to and including the next cluster exit. If AND = 0, exit current cluster.
skip all entries up to and including the entry with AND = 0. If matched and CLE = 1, enter cluster of entries,
otherwise, skip all entries up to and including the entry with CLE = 1 (cluster exit).
Figure 15-28. Receive Queue Filer Table Control Register Definition
—
Table 15-31. RQFAR Field Descriptions
Table 15-32. RQFCR Field Descriptions
Section 15.6.5.1, “Receive Queue
15 16
All zeros
Description
Description
Q
21
CLE REJ AND CMP —
22
23
Filer.” The word accessed
24
Freescale Semiconductor
25 26 27 28
Access: Read/Write
PID
31