R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 990

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
(2)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
The result is obtained in CRCDOR.
(3)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the
bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC
operation result is additionally written to the bytes to which CRC operation is to be performed, the
CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in
CRCCR (G1 and G0 bits) are set to 0 and 1, respectively, the lower byte of this register contains
the result.
Rev. 2.00 Oct. 21, 2009 Page 956 of 1454
REJ09B0498-0200
Bit
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
CRC Data Input Register (CRCDIR)
CRC Data Output Register (CRCDOR)
Bit Name
G1
G0
R/W
R/W
R/W
7
0
7
0
7
0
Initial
Value
0
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
Description
CRC Generating Polynomial Select:
Selects the polynomial.
00: Reserved
01: X
10: X
11: X
R/W
R/W
R/W
8
16
16
4
0
4
0
4
0
+ X
+ X
+ X
2
15
12
+ X + 1
+ X
+ X
R/W
R/W
R/W
2
5
3
0
3
0
3
0
+ 1
+ 1
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0

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