R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 402

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this
mode, indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby mode.
Note that the BACK and BREQO pins are both in the high-impedance state in software standby
mode.
(5)
The CBR refresh or auto-refresh cycle cannot be performed while the external bus is released.
When a CBR-refresh or an auto-refresh cycle is requested, the BREQO signal can be output by
setting the BREQOE bit in BCR1 to 1.
(6)
When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK
signals may go low simultaneously.
This will occur if the next external access request occurs while internal bus arbitration is in
progress after the chip samples a low level of the BREQ signal.
(7)
In single-chip activation mode, the setting of the RFSHE bit in REFCR should be made after
setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes.
(8)
The setting of bits RTCK2 to RTCK0 in REFCR should be made after RTCNT and RTCOR have
been set. When changing RTCNT and RTCOR, the counter operation should be halted. When
changing bits RTCK2 to RTCK0, external access and external bus release by the EXDMAC
should be prohibited. The write data buffer function should be used after the write data buffer
function is disabled and the external space is read.
(9)
When changing the RFSHE bit in REFCR from 1 to 0, a refresh cycle may be inserted until the bit
change is reflected. After this, when using RTCNT as an interval timer, the compare match flag
(CMF) may be set to 1. Therefore, confirm the state before setting the CMIE bit to 1.
Rev. 2.00 Oct. 21, 2009 Page 368 of 1454
REJ09B0498-0200
External Bus Release Function and CBR-Refresh or Auto-Refresh Cycle
BREQO Output Timing
Refresh Settings
Refresh Timer Settings
Switching Between Refresh Timer and Interval Timer