R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 262

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
Table 9.5
(2)
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions
as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits
or 16 bits, and the bus width for the byte control SRAM space is 16 bits.
The initial state of the bus width is specified by the operating mode.
If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as
16-bit access space, 16-bit bus mode is set.
(3)
Though the endian format of this LSI is big endian, data can be converted into little endian format
when reading or writing to the external address space.
Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in
ENDIANCR.
The initial state of each area is the big endian format.
Note that the data format for the areas used as a program area or a stack area should be big endian.
Rev. 2.00 Oct. 21, 2009 Page 228 of 1454
REJ09B0498-0200
Interface
DRAM interface
Synchronous DRAM interface
Interface
Basic interface
Byte control SRAM interface
Burst ROM interface
Address/data multiplexed I/O
interface
DRAM interface
Synchronous DRAM interface
Bus Width
Endian Format
Areas Specifiable for Each Interface
Description
Directly connected to DRAM
Directly connected to
synchronous DRAM
Related
Registers
SRAMCR
BROMCR
MPXCR
DRAMCR
0
O
O
O
⎯
⎯
⎯
1
O
O
O
⎯
⎯
⎯
2
O
O
⎯
⎯
O
O
Area Name
DRAM space
Synchronous DRAM space
3
O
O
⎯
O
⎯
⎯
Areas
4
O
O
⎯
O
⎯
⎯
5
O
O
⎯
O
⎯
⎯
6
O
O
⎯
O
⎯
⎯
7
O
O
⎯
O
⎯
⎯