R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1046

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 USB Function Module (USB)
(5)
The control-out status stage starts with an IN token from the host. When an IN-token is received at
the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer
request interrupt is generated. The application recognizes from this interrupt that the status stage
has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable
bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be
transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
Rev. 2.00 Oct. 21, 2009 Page 1012 of 1454
REJ09B0498-0200
Status Stage (Control-Out)
0-byte transmission to host
Set EP0i transmission
End of control transfer
(IFR0.EP0i TS = 1)
IN token reception
Figure 20.16 Status Stage (Control-Out) Operation
in EP0i FIFO?
complete flag
Valid data
USB function
Yes
ACK
NACK
No
Interrupt request
Interrupt request
Clear EP0i transmission
Write 1 to EP0i packet
End of control transfer
(TRG.EP0i PKTE = 1)
(IFR0.EP0i TR = 0)
Clear EP0i transfer
(IFR0.EP0i TS = 0)
complete flag
request flag
Application
enable bit

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