R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1312

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
4. Exit from deep software standby mode by the signal on the RES pin
5. Exit from deep software standby mode by the signal on the STBY pin
Note: * Supported only by the H8SX/1665M Group.
28.8.3
In deep software standby mode, the ports retain the states that were held during software standby
mode. The internal of the LSI is initialized by an internal reset caused by deep software standby
mode, and the reset exception handling starts as soon as deep software standby mode is canceled.
The following shows the port states at this time.
(1)
Pins for the address bus, bus control signals (CS0, AS, HWR, and LWR), and data bus operate
depending on the CPU.
(2)
Whether the ports are initialized or retain the states that were held during software standby mode
can be selected by the IOKEEP bit.
• When IOKEEP = 0
• When IOKEEP = 1
Rev. 2.00 Oct. 21, 2009 Page 1278 of 1454
REJ09B0498-0200
Clock oscillation and internal power supply start as soon as the signal on the RES pin is driven
low. At the same time, clock signals are supplied to the LSI. In this case, the RES pin has to be
held low until the clock oscillation has become stable. Once the signal on the RES pin is
driven high, the CPU starts reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Ports are initialized by an internal reset caused by deep software standby mode.
The port states that were held in deep software standby mode are retained regardless of the LSI
internal state though the internal of the LSI is initialized by an internal reset caused by deep
software standby mode. At this time, the port states that were held in software standby mode
are retained even if settings of I/O ports or peripheral modules are set. Subsequently, the
retained port states are released when the IOKEEP bit is cleared to 0 and operation is
performed according to the internal settings.
The IOKEEP bit is not initialized by an internal reset caused by canceling deep software
standby mode.
Pins for address bus, bus control and data bus
Pins other than address bus, bus control and data bus pins
Pin State on Exit from Deep Software Standby Mode