R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 590

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)
Figure 12.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
Rev. 2.00 Oct. 21, 2009 Page 556 of 1454
REJ09B0498-0200
DTC activation request
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERF:
DTCCR:
DTCVBR:
[Legend]
CPU interrupt request
Interrupt source clear
Interrupt controller
vector number
to DTCERF
DTCERA
DTCCR
request
must be set to 1.
(memory mapped)
External device
External
memory
8
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to F
DTC control register
DTC vector base register
peripheral
On-chip
On-chip
On-chip
module
ROM
RAM
Figure 12.1 Block Diagram of DTC
Bus controller
DTCVBR
REQ
ACK
DTC
Activation
Interrupt
Register
control
control
control
Bus interface
MRA
MRB
CRA
CRB
SAR
DAR