R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1044

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 USB Function Module (USB)
(3)
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (EP0oTS bit in
IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit,
empties the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 2.00 Oct. 21, 2009 Page 1010 of 1454
REJ09B0498-0200
Data Stage (Control-Out)
Data reception from host
OUT token reception
OUT token reception
(IFR0.EP0o TS = 1)
Set EP0o reception
Figure 20.14 Data Stage (Control-Out) Operation
complete flag
to TRG.EP0o
USB function
to TRG.EP0s
1 written
1 written
RDFN?
RDFN?
Yes
Yes
ACK
NACK
NACK
No
Interrupt request
No
receive data size register
data register (EPDR0o)
(TRG.EP0o RDFN = 1)
Read data from EP0o
Read data from EP0o
Clear EP0o reception
Write 1 to EP0o read
(IFR0.EP0o TS = 0)
complete flag
complete bit
(EPSZ0o)
Application

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