R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 17

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.10
9.11
9.12
9.13
9.14
DRAM Interface ............................................................................................................... 276
9.10.1
9.10.2
9.10.3
9.10.4
9.10.5
9.10.6
9.10.7
9.10.8
9.10.9
9.10.10 Controlling Byte and Word Accesses ............................................................... 286
9.10.11 Burst Access Operation..................................................................................... 288
9.10.12 Refresh Control................................................................................................. 294
9.10.13 DRAM Interface and Single Address Transfer by DMAC and EXDMAC ...... 299
Synchronous DRAM Interface ......................................................................................... 302
9.11.1
9.11.2
9.11.3
9.11.4
9.11.5
9.11.6
9.11.7
9.11.8
9.11.9
9.11.10 Controlling Write-Precharge Delay .................................................................. 314
9.11.11 Controlling Byte and Word Accesses ............................................................... 315
9.11.12 Fast-Page Access Operation ............................................................................. 317
9.11.13 Refresh Control................................................................................................. 323
9.11.14 Setting SDRAM Mode Register ....................................................................... 331
9.11.15 SDRAM Interface and Single Address Transfer by DMAC and EXDMAC .... 332
9.11.16 EXDMAC Cluster Transfer .............................................................................. 340
Idle Cycle.......................................................................................................................... 343
9.12.1
9.12.2
Bus Release....................................................................................................................... 356
9.13.1
9.13.2
9.13.3
Internal Bus....................................................................................................................... 360
9.14.1
Setting DRAM Space........................................................................................ 276
Address Multiplexing........................................................................................ 276
Data Bus............................................................................................................ 277
I/O Pins Used for DRAM Interface .................................................................. 277
Basic Timing..................................................................................................... 278
Controlling Column Address Output Cycle...................................................... 279
Controlling Row Address Output Cycle ........................................................... 280
Controlling Precharge Cycle............................................................................. 282
Wait Control ..................................................................................................... 283
Setting SDRAM space ...................................................................................... 302
Address Multiplexing........................................................................................ 303
Data Bus............................................................................................................ 303
I/O Pins Used for DRAM Interface .................................................................. 304
Basic Timing..................................................................................................... 305
CAS Latency Control........................................................................................ 307
Controlling Row Address Output Cycle ........................................................... 309
Controlling Precharge Cycle............................................................................. 311
Controlling Clock Suspend Insertion................................................................ 313
Operation .......................................................................................................... 343
Pin States in Idle Cycle ..................................................................................... 355
Operation .......................................................................................................... 356
Pin States in External Bus Released State......................................................... 357
Transition Timing ............................................................................................. 358
Access to Internal Address Space ..................................................................... 360
Rev. 2.00 Oct. 21, 2009 Page xv of xxxii

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