R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 301

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.9.4
Table 9.19 shows the pins used for the address/data multiplexed I/O Interface.
Table 9.19 I/O Pins for Address/Data Multiplexed I/O Interface
Note:
Pin
CSn
AS/AH
RD
LHWR/LUB
LLWR/LLB
D15 to D0
A23 to A0
WAIT
BS
RD/WR
*
I/O Pins Used for Address/Data Multiplexed I/O Interface
The AH output is multiplexed with the AS output. At the timing that an area is specified
as address/data multiplexed I/O, this pin starts to function as the AH output meaning
that this pin cannot be used as the AS output. At this time, when other areas set to the
basic bus interface is accessed, this pin does not function as the AS output. Until an
area is specified as address/data multiplexed I/O, be aware that this pin functions as
the AS output.
When Byte
Control
SRAM is
Specified
CSn
AH*
RD
LHWR
LLWR
D15 to D0
A23 to A0
WAIT
BS
RD/WR
Name
Chip select
Address hold
Read strobe
Low-high write Output
Low-low write Output
Address/data
Address
Wait
Bus cycle start Output
Read/write
I/O
Output
Input/
Output
Input
Output
Output
output
Output
Function
Chip select (n = 3 to 7) when area n is specified as the
address/data multiplexed I/O space
Signal to hold an address when the address/data
multiplexed I/O space is specified
space is being read
Strobe signal indicating that the upper byte (D15 to
D8) is valid when the address/data multiplexed I/O
space is written
Strobe signal indicating that the lower byte (D7 to D0)
is valid when the address/data multiplexed I/O space is
written
Address and data multiplexed pins for the
address/data multiplexed I/O space.
Only D7 to D0 are valid when the 8-bit space is
specified. D15 to D0 are valid when the 16-bit space is
specified.
Address output pin
Wait request signal used when the external address
space is accessed
Signal to indicate the bus cycle start
Signal indicating the data bus input or output direction
Signal indicating that the address/data multiplexed I/O
Rev. 2.00 Oct. 21, 2009 Page 267 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200