R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 16

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.6
9.7
9.8
9.9
Rev. 2.00 Oct. 21, 2009 Page xiv of xxxii
9.5.3
9.5.4
9.5.5
9.5.6
Basic Bus Interface ........................................................................................................... 240
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
9.6.7
Byte Control SRAM Interface .......................................................................................... 253
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
9.7.8
Burst ROM Interface ........................................................................................................ 261
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.8.7
Address/Data Multiplexed I/O Interface........................................................................... 266
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
9.9.10
Chip Select Signals ........................................................................................... 226
External Bus Interface ...................................................................................... 227
Area and External Bus Interface ....................................................................... 232
Endian and Data Alignment.............................................................................. 237
Data Bus ........................................................................................................... 240
I/O Pins Used for Basic Bus Interface .............................................................. 240
Basic Timing..................................................................................................... 241
Wait Control ..................................................................................................... 247
Read Strobe (RD) Timing................................................................................. 249
Extension of Chip Select (CS) Assertion Period............................................... 250
DACK and EDACK Signal Output Timing...................................................... 252
Byte Control SRAM Space Setting................................................................... 253
Data Bus ........................................................................................................... 253
I/O Pins Used for Byte Control SRAM Interface ............................................. 254
Basic Timing..................................................................................................... 255
Wait Control ..................................................................................................... 257
Read Strobe (RD) ............................................................................................. 259
Extension of Chip Select (CS) Assertion Period............................................... 259
DACK and EDACK Signal Output Timing...................................................... 259
Burst ROM Space Setting................................................................................. 261
Data Bus ........................................................................................................... 261
I/O Pins Used for Burst ROM Interface............................................................ 262
Basic Timing..................................................................................................... 263
Wait Control ..................................................................................................... 265
Read Strobe (RD) Timing................................................................................. 265
Extension of Chip Select (CS) Assertion Period............................................... 265
Address/Data Multiplexed I/O Space Setting ................................................... 266
Address/Data Multiplex.................................................................................... 266
Data Bus ........................................................................................................... 266
I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 267
Basic Timing..................................................................................................... 268
Address Cycle Control...................................................................................... 270
Wait Control ..................................................................................................... 271
Read Strobe (RD) Timing................................................................................. 271
Extension of Chip Select (CS) Assertion Period............................................... 273
DACK and EDACK Signal Output Timing...................................................... 275