R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 969

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.7.4
Only the internal clock generated by the on-chip baud rate generator can be used as a transfer
clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a
frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings
(the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the
falling edge of the start bit is sampled using the base clock in order to perform internal
synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the
base clock so that it can be latched at the middle of each bit as shown in figure 19.28. The
reception margin here is determined by the following formula.
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is
determined by the formula below.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 19.28 Receive Data Sampling Timing in Smart Card Interface Mode
[Legend]
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M =
M = | (0.5 –
Receive Data Sampling Timing and Reception Margin
( 0.5 –
2 × 372
(When Clock Frequency is 372 Times the Bit Rate)
2N
1
0
186 clock
1
) – (L – 0.5) F –
cycles
372 clock cycles
) × 100% = 49.866%
185
Start bit
| D – 0.5 |
371
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
N
0
(1 + F ) | × 100%
D0
Rev. 2.00 Oct. 21, 2009 Page 935 of 1454
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371 0
REJ09B0498-0200
D1