R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1327

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
28.12
Usage Notes
28.12.1 I/O Port Status
In software standby mode or deep software standby mode, the I/O port states are retained.
Therefore, there is no reduction in current drawn due to output currents when high-level signals
are being output.
28.12.2 Current Consumption during Oscillation Settling Standby Period
Current consumption increases during the oscillation settling standby period.
28.12.3 Module Stop State of EXDMAC, DMAC, or DTC
Depending on the operating state of the EXDMAC, DMAC, and DTC, bits MSTPA14,
MSTPA13, and MSTPA12 may not be set to 1, respectively. The module stop state setting for the
EXDMAC, DMAC, or DTC should be carried out only when the EXDMAC, DMAC, or DTC is
not activated.
For details, refer to section 10, DMA Controller (DMAC), section 11, EXDMA Controller
(EXDMAC), and section 12, Data Transfer Controller (DTC).
28.12.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in a module stop state. Consequently, if the
module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be
disabled before entering a module stop state.
28.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
Rev. 2.00 Oct. 21, 2009 Page 1293 of 1454
REJ09B0498-0200