R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 587

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4. Activation Source Acceptance
5. Conflict in Cluster Transfer
6. Cluster Transfer Mode and Endian
At the start of activation source acceptance, low level sensing is used for both falling edge
sensing and low level sensing on the EDREQ. Therefore, a request is accepted in the case of a
low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the
transfer-enabled state.
At EXDMAC activation, low level on the EDREQ pin must not remain at the end of the
previous transfer.
In cluster transfer mode, the same cluster buffer is used for all channels. When more than one
cluster transfer conflicts, the cluster buffer register holds the value of the last cluster transfer.
When the transfer between the transfer source/destination and the cluster buffer conflicts with
another cluster transfer, the transferred data in the cluster buffer may be overwritten by another
channel cluster transfer. Therefore, in the cluster transfer mode (single address mode), do not
set the cluster transfer mode for any other channels.
In cluster transfer mode, only a transfer to the areas in the big endian format is supported.
When cluster transfer mode is specified, do not specify the areas in the little endian format for
EDSAR and EDDAR. For details on the endian, see section 9, Bus Controller (BSC).
Rev. 2.00 Oct. 21, 2009 Page 553 of 1454
Section 11 EXDMA Controller (EXDMAC)
REJ09B0498-0200