R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 401

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.17
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
9.18
(1)
The BSC registers must be specified before accessing the external address space. In on-chip ROM
disabled mode, the BSC registers must be specified before accessing the external address space for
other than an instruction fetch access.
(2)
The burst read-burst write mode of synchronous DRAM is not supported.
When setting the mode register of synchronous DRAM, the burst read-single write mode must be
selected and the burst length must be 1.
(3)
In this LSI, if the ACSE bit in MSTPCRA is set to 1 and a SLEEP instruction is executed to enter
the sleep state after shutting off the clocks to all peripheral modules (MSTPCRA and MSTPCRB
= H'FFFFFFF) or allowing operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB
= H'F[C to F]FFFFFF), the all-module-clock-stop mode is entered in which the clock for the bus
controller and I/O ports is also stopped. For details, see section 28, Power-Down Modes.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction
to place the chip in all-module-clock-stop mode is executed in the external bus released state, the
transition to all-module-clock-stop mode is deferred and performed until after the bus is
recovered.
(4)
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Setting Registers
Mode Settings
External Bus Release Function and All-Module-Clock-Stop Mode
External Bus Release Function and Software Standby Mode
Bus Controller Operation in Reset
Usage Notes
Rev. 2.00 Oct. 21, 2009 Page 367 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200