R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 213

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters; CPU, DMAC, EXDMAC, and DTC.
9.1
• Manages external address space in area units
• Basic bus interface
• Byte control SRAM interface
• Burst ROM interface
• Address/data multiplexed I/O interface
Manages the external address space divided into eight areas
Chip select signals (CS0 to CS7) can be output for each area
Bus specifications can be set independently for each area
8-bit access or 16-bit access can be selected for each area
DRAM, synchronous DRAM, burst ROM, byte control SRAM, or address/data multiplexed
I/O interface can be set
An endian conversion function is provided to connect a device of little endian
This interface can be connected to the SRAM and ROM
2-state access or 3-state access can be selected for each area
Program wait cycles can be inserted for each area
Wait cycles can be inserted by the WAIT pin.
Extension cycles can be inserted while CSn is asserted for each area (n = 0 to 7)
The negation timing of the read strobe signal (RD) can be modified
Byte control SRAM interface can be set for areas 0 to 7
The SRAM that has a byte control pin can be directly connected
Burst ROM interface can be set for areas 0 and 1
Burst ROM interface parameters can be set independently for areas 0 and 1
Address/data multiplexed I/O interface can be set for areas 3 to 7
Features
Section 9 Bus Controller (BSC)
Rev. 2.00 Oct. 21, 2009 Page 179 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200