R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 19

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC) ....................................................449
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10 Usage Notes ...................................................................................................................... 552
Features............................................................................................................................. 449
Input/Output Pins.............................................................................................................. 452
Registers Descriptions ...................................................................................................... 453
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Transfer Modes ................................................................................................................. 476
11.4.1
11.4.2
Mode Operation ................................................................................................................ 478
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
11.5.9
11.5.10 Bus Cycles in Dual Address Mode ................................................................... 502
11.5.11 Bus Cycles in Single Address Mode................................................................. 511
11.5.12 Operation Timing in Each Mode ...................................................................... 516
Operation in Cluster Transfer Mode ................................................................................. 527
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
Ending EXDMA Transfer................................................................................................. 544
Relationship among EXDMAC and Other Bus Masters................................................... 547
11.8.1
11.8.2
Interrupt Sources............................................................................................................... 549
EXDMA Source Address Register (EDSAR)................................................... 455
EXDMA Destination Address Register (EDDAR)........................................... 456
EXDMA Offset Register (EDOFR).................................................................. 457
EXDMA Transfer Count Register (EDTCR).................................................... 458
EXDMA Block Size Register (EDBSR)........................................................... 459
EXDMA Mode Control Register (EDMDR) .................................................... 460
EXDMA Address Control Register (EDACR) ................................................. 469
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 475
Ordinary Modes ................................................................................................ 476
Cluster Transfer Modes..................................................................................... 477
Address Modes ................................................................................................. 478
Transfer Modes ................................................................................................. 481
Activation Sources............................................................................................ 486
Bus Mode.......................................................................................................... 487
Extended Repeat Area Function ....................................................................... 488
Address Update Function Using Offset ............................................................ 491
Registers during EXDMA Transfer Operation ................................................. 495
Channel Priority Order...................................................................................... 500
Basic Bus Cycles .............................................................................................. 501
Address Mode ................................................................................................... 527
Setting of Address Update Mode ...................................................................... 532
Caution for Combining with Extended Repeat Area Function ......................... 533
Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 533
Operation Timing in Cluster Transfer Mode .................................................... 536
CPU Priority Control Function Over EXDMAC .............................................. 547
Bus Arbitration with Another Bus Master ........................................................ 548
Rev. 2.00 Oct. 21, 2009 Page xvii of xxxii