R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 544

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(6)
When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be
delayed one cycle later.
Figure 11.33 shows an example of normal transfer mode transfer activated by the EDREQ pin low
level with NRD = 1 specified.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes
when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low
level sampling is performed again. This sequence of operations is repeated until the end of the
transfer.
Rev. 2.00 Oct. 21, 2009 Page 510 of 1454
REJ09B0498-0200
Bφ
EDREQ
Address
bus
Channel
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle plus one cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
Figure 11.33 Example of Normal Transfer Mode Transfer Activated
[1]
Request
Bus release
Minimum 3 cycles
[2]
by EDREQ Pin Low Level with NRD = 1 Specified
Request clearance period
[3]
EXDMA read EXDMA write
Transfer
source
destination
Transfer
Extended request
clearance period
specified by NRD
Acceptance resumed
[4]
Bus release
Minimum 3 cycles
Request
[5]
Request clearance period
[6]
EXDMA read EXDMA write
Transfer
source
destination
Acceptance resumed
Transfer
Extended request
clearance period
specified by NRD
Bus release
[7]