R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 308

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
When consecutively reading from the same area connected to a peripheral LSI whose data hold
time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip
select assertion period extension cycle after the access cycle can avoid the data conflict.
Figure 9.36 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in
(b).
Rev. 2.00 Oct. 21, 2009 Page 274 of 1454
REJ09B0498-0200
Bφ
Address bus
CS
AH
RD
Data bus
Bφ
Address bus
CS
AH
RD
Data bus
Figure 9.36 Consecutive Read Accesses to Same Area
(a) Without CS assertion period extension cycle (CSXTn = 0)
(b) With CS assertion period extension cycle (CSXTn = 1)
(Address/Data Multiplexed I/O Space)
Bus cycle A
Bus cycle A
Data hold time is long.
Bus cycle B
Data conflict
Bus cycle B