R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 568

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(2)
Figure 11.62 shows an example of cluster transfer mode transfer activated by the EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing
is started. If EDREQ pin high level sampling is completed by the end of the last cluster write
cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
Rev. 2.00 Oct. 21, 2009 Page 534 of 1454
REJ09B0498-0200
Bφ
EDREQ
Address bus
EXDMA control
Channel
[1]
[2] [5]
[3] [6]
[4] [7]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle starts; EDREQ pin high level sampling is started at rise of Bφ.
When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Falling Edge Activation Timing
Figure 11.62 Example of Cluster Transfer Mode Transfer Activated
[1]
Request
Minimum 3 cycles
Bus release
[2]
Consecutive read
[3]
Request clearance period
Transfer source
by EDREQ Pin Falling Edge
One cluster transfer
Consecutive write
Transfer destination
[4]
Request
Minimum 3 cycles
Bus release
[5]
Consecutive read
[6]
Transfer source
Request clearance period
One cluster transfer
Consecutive write
Transfer destination
[7]