R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1328

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
28.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0)
When the input buffers for the P10/IRQ0-A to P13/IRQ3-A pins are enabled by setting the
DIRQnE bits (n = 3 to 0) in DSPIER to 1, the PnICR settings corresponding to these pins are
invalid. Therefore, note that external inputs to these pins, of which states are reflected on the
DIRQnF bits, are also input to the interrupt controller, peripheral modules and I/O ports, after the
DIRQnE bits (n = 3 to 0) are set to 1.
28.12.7 Conflict between a transition to deep standby mode and interrupts
If a conflict among the transition to deep software standby mode and generation of software
standby mode clearing source occurs, a transition to deep software standby mode is not made but
the software standby mode clearing sequence is executed. In this case, an interrupt exception
handling for the input interrupt starts after the oscillation settling time for software standby mode
(set by the STS4 to STS0 bits in SBYCR) has elapsed.
Note that if a conflict between a deep software standby mode transition and NMI interrupt occurs,
the NMI interrupt exception handling routine is required.
If a conflict among a deep software standby mode transition, the IRQ0 to IRQ11 interrupts, 32K
timer interrupt, and voltage-monitoring interrupt* occurs, a transition to deep software standby
mode can be made without executing the interrupt execution handling by clearing the SSIn bits in
SSIER to 0 beforehand.
Note: * Supported only by the H8SX/1665M Group
28.12.8 Bφ/SDRAMφ Output State
Bφ/SDRAMφ output is undefined for a maximum of one cycle immediately after deep software
standby mode is canceled with the IOKEEP bit cleared to 0 or immediately after the IOKEEP bit
is cleared after cancellation of deep software standby mode with the IOKEEP bit set to 1.
However, Bφ/SDRAMφ can be normally output by setting the IOKEEP, PSTOP1, and PSTP0 bits
to 1. For details, see section 28.8.4, Bφ/SDRAMφ Operation after Exit from Deep Software
Standby Mode.
Rev. 2.00 Oct. 21, 2009 Page 1294 of 1454
REJ09B0498-0200