R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 299

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.8.5
As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT
pin can be used in the initial cycle (full access) on the burst ROM interface. See section 9.6.4,
Wait Control. Wait cycles cannot be inserted in a burst cycle.
9.8.6
When the burst ROM space is read by the CPU or EXDMAC cluster transfer, the RDNCR setting
for the corresponding space is invalid.
The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface.
9.8.7
In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus
interface.
For the burst ROM space, the burst access can be enabled only in read access by the CPU or
EXDMAC cluster transfer. In this case, the setting of the corresponding CSXTn bit in CSACR is
ignored and an extension cycle can be inserted only before the full access cycle. Note that no
extension cycle can be inserted before or after the burst access cycles.
In accesses other than read accesses by the CPU and EXDMAC cluster transfer, the burst ROM
space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted
before and after the burst access cycles.
Wait Control
Read Strobe (RD) Timing
Extension of Chip Select (CS) Assertion Period
Rev. 2.00 Oct. 21, 2009 Page 265 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200