R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 621

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing
2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing
3. Locate the TPU transfer information consecutively after the NDR transfer information.
4. Set the start address of the NDR transfer information to the DTC vector address.
5. Set the bit corresponding to the TGIA interrupt in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
12.7.3
By executing a second data transfer and performing re-setting of the first data transfer only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is
assumed to have been set to start at lower address H'0000. Figure 12.16 shows the chain transfer
when the counter value is 0.
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set
MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start
address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL.
CRB can be set to any value.
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA
address in DAR, and the data table size in CRA. CRB can be set to any value.
interrupt with TIER.
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
Chain Transfer when Counter = 0
Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Oct. 21, 2009 Page 587 of 1454
REJ09B0498-0200