R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1067

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
7
6
5
4
3
2
1
0
Bit Name
BBSY
SCP
SDAO
⎯
SCLO
⎯
IICRST
⎯
Initial
Value
0
1
1
1
1
1
0
1
R/W
R/W
R/W
R
R/W
R
⎯
R/W
⎯
Description
Bus Busy
This bit indicates whether the I2C bus is occupied or
released and to issue start and stop conditions in master
mode. This bit is set to 1 when the SDA level changes
from high to low under the condition of SCL = high,
assuming that the start condition has been issued. This
bit is cleared to 0 when the SDA level changes from low
to high under the condition of SDA = high, assuming that
the stop condition has been issued. Follow this procedure
also when re-transmitting a start condition. To issue a
start or stop condition, use the MOV instruction.
Start/Stop Condition Issue
This bit controls the issuance of start or stop condition in
master mode.
To issue a start condition, write 1 to BBSY and 0 to SCP.
A re-transmit start condition is issued in the same way. To
issue a stop condition, write 0 to BBSY and 0 to SCP.
This bit is always read as 1. If 1 is written, the data is not
stored.
This bit monitors the output level of SDA.
0: When reading, the SDA pin outputs a low level
1: When reading the SDA pin outputs a high level
Reserved
The write value should always be 1.
This bit monitors the SCL output level.
When reading and SCLO is 1, the SCL pin outputs a high
level. When reading and SCLO is 0, the SCL pin outputs
a low level.
Reserved
This bit is always read as 1.
IIC Control Module Reset
This bit reset the IIC control module except the I
registers. If hang-up occurs because of communication
failure during I
control module can be reset without setting ports and
initializing the registers.
Reserved
This bit is always read as 1.
2
C operation, by setting this bit to 1, the I
Rev. 2.00 Oct. 21, 2009 Page 1033 of 1454
Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0498-0200
2
C
2
C