R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 231

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note: When external bus release is enabled or input by the WAIT pin is enabled, make sure to set
Bit
9
8
7
6
5 to 0
the ICR bit to 1. For details, see section 13, I/O Ports.
Bit Name
WDBE
WAITE
DKC
EDKC
⎯
Initial Value R/W
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R
Description
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle and a DMAC single address
transfer cycle.
The changed setting may not affect an external
access immediately after the change.
0: Write data buffer function not used
1: Write data buffer function used
WAIT Pin Enable
Selects enabling/disabling of wait input by the WAIT
pin. When area 2 is specified as the synchronous
DRAM space, the setting of this bit does not affect
the synchronous DRAM space access operation.
0: Wait input by WAIT pin disabled
1: Wait input by WAIT pin enabled
For details, see section 13, I/O Ports.
DACK Control
Selects the timing of DMAC transfer acknowledge
signal assertion.
0: DACK signal is asserted at the Bφ falling edge
1: DACK signal is asserted at the Bφ rising edge
EDACK Control
Controls the assertion timing of an acknowledge
signal for an EXDMAC transfer.
0: EDACK signal asserted at the falling edge of Bφ
1: EDACK signal asserted at the rising edge of Bφ
Reserved
These are read-only bits and cannot be modified.
WAIT pin can be used as I/O port
Rev. 2.00 Oct. 21, 2009 Page 197 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200