R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 255

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.5
9.5.1
Table 9.2 shows the pin configuration of the bus controller and table 9.3 shows the pin functions
on each interface.
Table 9.2
Name
Bus cycle start
Address strobe/
address hold
Read strobe
Read/write
Low-high write/
lower-upper byte
select
Low-low write/
lower-lower byte
select
External Bus
Input/Output Pins
Pin Configuration
Symbol
BS
AS/AH
RD
RD/WR
LHWR/LUB
LLWR/LLB
I/O
Output
Output
Output
Output
Output
Output
Function
Signal indicating that the bus cycle has started
•
•
Strobe signal indicating that the basic bus, byte control
SRAM, burst ROM, or address/data multiplexed I/O space
is being read
•
•
•
•
•
•
Strobe signal indicating that the basic bus, byte control
SRAM, or burst ROM space is accessed and address
output on address bus is enabled
Signal to hold the address during access to the
address/data multiplexed I/O interface
Signal indicating the input or output direction
Write enable signal of the SRAM during access to the
byte control SRAM space
Strobe signal indicating that the basic bus, burst ROM,
or address/data multiplexed I/O space is written to,
and the upper byte (D15 to D8) of data bus is enabled
Strobe signal indicating that the byte control SRAM
space is accessed, and the upper byte (D15 to D8) of
data bus is enabled
Strobe signal indicating that the basic bus, burst ROM,
or address/data multiplexed I/O space is written to,
and the lower byte (D7 to D0) of data bus is enabled
Strobe signal indicating that the byte control SRAM
space is accessed, and the lower byte (D7 to D0) of
data bus is enabled
Rev. 2.00 Oct. 21, 2009 Page 221 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200