R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1304

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 28 Power-Down Modes
28.5
28.5.1
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep
mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are
retained. Other peripheral functions do not stop.
28.5.2
Sleep mode is exited by any interrupt, signals on the RES or STBY pin, and a reset caused by a
watchdog timer overflow, a voltage monitoring reset*, or a power-on reset*.
• Exit from sleep mode by interrupt
• Exit from sleep mode by RES pin
• Exit from sleep mode by STBY pin
• Exit from sleep mode by reset caused by watchdog timer overflow
• Exit from voltage monitoring reset*
• Exit from power-on reset*
Note: * Supported only by the H8SX/1665M Group.
Rev. 2.00 Oct. 21, 2009 Page 1270 of 1454
REJ09B0498-0200
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high makes the CPU start the reset exception processing.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Sleep mode is exited by an internal reset caused by a watchdog timer overflow.
Sleep mode is exited by a voltage monitoring reset of the voltage detection circuit.
Sleep mode is exited by a power-on reset.
Sleep Mode
Entry to Sleep Mode
Exit from Sleep Mode

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