R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1049

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one
FIFO is empty, the EP2EMPTY bit in IFR0 is set to 1. When ACK is returned from the host after
data transmission is completed, the FIFO used in the data transmission becomes empty. If the
other FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and
disable interrupt requests.
20.5.7
EP3 Interrupt-In Transfer
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is
referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 20.19 Operation of EP3 Interrupt-In Transfer
Data transmission to host
Set EP3 transmission
(IFR1.EP3 TS = 1)
IN token reception
complete flag
USB function
in EP3FIFO?
Valid data
Yes
ACK
NACK
No
Interrupt request
Clear EP3 transmission
Write data to EP3 data
Write data to EP3 data
(TRG.EP3 PKTE = 1)
Write 1 to EP3 packet
Write 1 to EP3 packet
(TRG.EP3 PKTE = 1)
(IFR1.EP3 TS = 0)
register (EPDR3)
register (EPDR3)
for transmission
for transmission
complete flag
Rev. 2.00 Oct. 21, 2009 Page 1015 of 1454
Is there data
Is there data
enable bit
enable bit
to host?
to host?
Section 20 USB Function Module (USB)
Application
Yes
Yes
No
No
REJ09B0498-0200

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