R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1282

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
Rev. 2.00 Oct. 21, 2009 Page 1248 of 1454
REJ09B0498-0200
Notes: 1. NMI, IRQ0 to IRQ11, 8-bit timer interrupt, watchdog timer interrupt, 32K timer interrupt, and voltage monitoring interrupt*
[Legend]
Note:
Subclock operation
(CK32K = 1)
Main clock operation
(CK32K = 0)
2. NMI, IRQ0 to IRQ11, 32K timer interrupt, USB suspend/resume interrupt, and voltage monitoring interrupt*
3. The SLPIE bit is cleared to 0.
4. NMI, IRQ0-A to IRQ3-A, 32K timer interrupts, USB suspend/resume interrupts, and voltage monitoring interrupt*
5. If a conflict between a transition to deep software standby mode and generation of software standby mode
6. Supported only by the H8SX/1665M Group.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low.
CK32K = 0
clearing source occurs, a mode transition may be made from software standby mode to program execution state
Note that the 8-bit timer interrupt is valid when the MSTPCRA9 or MSTPCRA8 bit is cleared to 0.
Note that IRQ is valid only when the corresponding bit in SSIER is set to 1.
Note that IRQ, 32K timer, and voltage monitoring interrupt*
through execution of interrupt exception handling. In this case, a transition to deep software standby mode is not
made. For details, refer to section 28.12, Usage Notes.
Program execution state
Program execution state
Transition after exception handling
RES pin = Low
Reset state
RES pin = High
CK32K = 1
SLEEP instruction*
SLEEP instruction
Figure 28.1 Mode Transitions
STBY pin = High
RES pin = Low
WAKE32K = 0
and Interrupt
3
(SSBY =1)
Interrupt
All interrupts
Interrupt
(SSBY =1)
WAKE32K = 1
and Interrupt
All interrupts
Interrupt
6
are valid only when the corresponding bit in DPSIER is set to 1.
*
(DPSBY = 0
and no interrupt
is generated)
2
*
*
*
2
1
1
*
2
SSBY = 0, ACSE = 1
MSTPCR = H'F[C-F]FFFFFF
SSBY = 0, ACSE = 1
MSTPCR = H'F[C-F]FFFFFF
Program halted state
Program halted state
Internal reset state
STBY pin = Low
All-module-clock-
All-module-clock-
standby mode
Deep software
Deep software
standby mode
standby mode
standby mode
standby mode
Hardware
Sleep mode
Sleep mode
stop mode
stop mode
SSBY = 0
SSBY = 0
Software
Software
(DPSBY = 1
and no interrupt
is generated*
(DPSBY = 1
and no interrupt
is generated*
5
5
6
)
)
(DPSBY = 0
and no interrupt
is generated)
.
Interrupt
Interrupt
6
.
*
*
4
4
6
.