R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 230

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.2.7
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the WAIT pin input.
Rev. 2.00 Oct. 21, 2009 Page 196 of 1454
REJ09B0498-0200
Bit
15
14
13, 12
11, 10
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
BRLE
BREQOE
Bus Control Register 1 (BCR1)
BRLE
DKC
R/W
R/W
15
0
7
0
Initial Value R/W
0
0
All 0
All 0
BREQOE
EDKC
R/W
R/W
14
0
6
0
13
R/W
R/W
R
R/W
R
R
0
5
0
Description
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
1: External bus release enabled*
For details, see section 13, I/O Ports.
BREQO Pin Enable
Controls outputting the bus request signal (BREQO)
to the external bus master in the external bus
released state when an internal bus master performs
an external address space access.
0: BREQO output disabled
1: BREQO output enabled
Reserved
These are read-only bits and cannot be modified.
Reserved
These bits are always read as 0. The write value
should always be 0.
12
R
R
0
4
0
BREQO pin can be used as I/O port
BREQ, BACK, and BREQO pins can be used as
I/O ports
R/W
11
R
0
3
0
R/W
10
R
0
2
0
WDBE
R/W
R
9
0
1
0
WAITE
R/W
R
8
0
0
0

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