R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1211

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

25.9.2
The software protection protects the flash memory against programming/erasure by disabling
download of the programming/erasing program, using the key code, and by the RAMER setting.
Table 25.14 Software Protection
25.9.3
Error protection is a mechanism for aborting programming or erasure when a CPU runaway
occurs or operations not according to the programming/erasing procedures are detected during
programming/erasure of the flash memory. Aborting programming or erasure in such cases
prevents damage to the flash memory due to excessive programming or erasing.
If an error occurs during programming/erasure of the flash memory, the FLER bit in FCCS is set
to 1 and the error protection state is entered.
• When an interrupt request, such as NMI, occurs during programming/erasure.
• When the flash memory is read from during programming/erasure (including a vector read or
• When a SLEEP instruction is executed (including software-standby mode) during
• When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership
Item
Protection
by SCO bit
Protection
by FKEY
Emulation
protection
an instruction fetch).
programming/erasure.
during programming/erasure.
Software Protection
Error Protection
Description
The programming/erasing protection state is
entered when the SCO bit in FCCS is cleared to 0
to disable download of the programming/erasing
programs.
The programming/erasing protection state is
entered because download and
programming/erasure are disabled unless the
required key code is written in FKEY.
The programming/erasing protection state is
entered when the RAMS bit in the RAM emulation
register (RAMER) is set to 1.
Rev. 2.00 Oct. 21, 2009 Page 1177 of 1454
Download
O
O
O
Function to be Protected
Section 25 Flash Memory
Programming/
Erasing
O
O
O
REJ09B0498-0200