R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 168

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Interrupt Controller
Note:
7.3.5
ISCRH and ISCRL select the source that generates an interrupt request from IRQ15, IRQ14, and
IRQ11 to IRQ0 input.
Upon changing the setting of ISCR, IRQnF (n = 0 to 11, 14, 15) in ISR is often set to 1
accidentally through an internal operation. In this case, an interrupt exception handling is executed
if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from
occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then
the IRQnF in ISR should be cleared to 0.
Rev. 2.00 Oct. 21, 2009 Page 134 of 1454
REJ09B0498-0200
Bit
7
6
5
4
3
2
1
0
*
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
Bit Name
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Supported only by the H8SX/1665M Group.
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
IRQ7 Enable
The IRQ7 interrupt request is enabled when this bit is 1.
IRQ6 Enable
The IRQ6 interrupt request is enabled when this bit is 1.
IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit is 1.
IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is 1.
IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is 1.
IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is 1.
IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is 1.
IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is 1.